The term EPROM stands for electronically programmable read-only memory. In contrast to random access memories (RAMs), an EPROM comprises a memory, which retains information, even if the power supply to the memory is switched off. The EPROM device commonly comprises a field effect transistor having a source, a drain and a conduction channel between the source and drain. Additionally, the field effect transistor has a gate floating above channel. The floating gate is electrically isolated. Information is stored by injecting charges on the floating gate. Due to its isolation, the charges remain on the floating gate, even if the power supply is switched off. The charges on the floating gate effect the conductance channel between the source and the drain of the field effect transistor. The information may be retrieved from the memory device by measuring the current flowing between the source and the drain.
A top view of a more advanced EPROM device, called a Single Poly EPROM device, is shown in FIG. 1. The Single Poly EPROM device of FIG. 1 comprises a floating gate 10, a control gate 12, a source 16 and a drain 18. Source 16, drain 18 and floating gate 10 form a field effect transistor, wherein the floating gate 10 represents the gate of the field effect transistor. The channel between source 16 and drain 18 is covered by a part of the floating gate 10 in FIG. 1. A back gate contact 14b, a drain contact 14D and a source contact 14S are connected to a back gate 10, the source 18 and the drain 16, respectively. The peculiarity of the Single Poly EPROM device is that the control gate 12 is not formed by a conductive layer on top of the floating gate 10, but by a doped semiconductor region underlying part of the floating gate 10. The floating gate 10 is made out of a poly-silicon layer on top of both the channel of the field effect transistor and the control gate 12. Two control gate contacts 14C are connected to the control gate 12 (although a simple control gate is sufficient for functionality).
FIG. 2 shows a schematic cross section of the Single Poly EPROM device of FIG. 1. The floating gate 10 is situated above both the control gate 12 and the channel between source 16 and drain 18. A back gate 20 shown in FIG. 2 has the same purpose as in standard MOS transistors. Reference sign C1 depicts the capacitance between the floating gate 10 and the control gate 12 of the Single Poly EPROM device shown in FIG. 2. Single Poly EPROM devices can be programmed either through hot carrier injection or Fowler-Nordheim tunneling. A thin gate oxide is provided as isolator between the floating gate 10 and the channel region. The channel region can be used for tunneling between the floating gate 10 and source 16/drain 18.
FIG. 3 illustrates the configuration of a conventional memory array consisting of Single Poly EPROM devices 32 and select transistors 30. One Single Poly EPROM device 32 connected to a selected transistor 30 forms a memory cell in the array. The memory cells are grouped in columns Coll, Colt and rows ROW1, ROW2. The select transistor 30 is a high voltage transistor, which is connected to the Single Poly EPROM device in order to protect the floating gate 10 against the high programming voltage. Otherwise, a high voltage applied to the drain 18 of the Single Poly EPROM device 32 during erasing would also appear at the drain 18 of the other unselected cells in the same memory column COL1, COL2. Consequently, the memory cell must consist of two transistors 30 and 32 as shown in FIG. 3. This select transistor 30 is needed to prevent programming if the transistor is not selected. If each Single Poly EPROM cell has to be programmable individually, then each Single Poly EPROM cell has to contain one select transistor 30. Therefore, the total area of the array is significantly increased by the high voltage select transistors 30.